ADVISORY/ 0-In to Present Paper at DVCon on Using Assertion-Based Verification to Verify Clock Domain Crossing Signals

SAN JOSE, Calif. - February 20, 2003 - Today 0-In Design Automation, the Assertion-Based Verification company, announces that key members of its engineering staff will present a paper at DVCon on using assertion-based verification to verify clock domain crossing signals.

Chris Ka-kei Kwok, Vijay Vardhan Gupta, and 0-In co-founder Dr. Tai Ly will speak at 9:30am on Monday, February 24. Their paper will describe an approach for finding the serious clock domain crossing issues that would otherwise be found only in silicon. This approach combines netlist analysis, inference of design intent, assertions in an assertion library, simulation, and formal verification. Demonstrations of the design examples outlined in the presentation will be available in Booth #202 during the conference.

The paper will be available on 0-In's website on March 31, 2003.

About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle - from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.

Contacts:

0-In Design Automation
Steve White
408-487-3649
swhite@0-in.com

Cayenne Communication
Linda Marchant
919-683-9545
linda.marchant@cayennecom.com